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We have used the even-parity example to illustrate the general sequential circuit design process. But we did not complete the design (see Example 4.1 on page 132). In this exercise, complete the design of this circuit.


Example 4.1


Even-parity checker. Parity is used to provide rudimentary error detection capability. For example, we can associate a parity bit for each 7-bit ASCII character transmitted. Even parity means that the total number of 1’s in the 8-bit group (7 data bits + 1 parity bit)


should be an even number. The receiver of the data also computes the parity and checks if the data have been received properly. For a properly received 8-bit datum, the computed parity bit should be 0. Parity provides single-bit error detection capability.

We have seen in Section 2.10.2 (see Figure 2.27 on page 77) that we can use XOR gates to generate even parity. However, this circuit is not useful for us if the data are coming serially, one bit at a time as on a modem line. If we want to use the XOR implementation, we need to convert the serial input data to parallel form. The other alternative is to design a sequential circuit that receives data in serial form and generates the parity bit.

A simple analysis leads us to the conclusion that the FSM needs to remember only one of two facts summarizing the past input sequence: whether the number of 1’s is odd or even. Thus, our FSM needs just two states as shown in Figure 4.23. In the FSM, state S0 represents the fact that the input sequence so far has an even number of 1’s. The odd number of 1’s is represented by state S1.

Now we have to look at the possible transitions between these two states. When the machine is in state S0, if a 1 is received, the machine should move to S1. Also, it should output a 1 as


the parity bit for the data it has received so far. This transition is shown in the figure with label 1/1 to represent the fact that the input is 1 and the output is also 1. On the other hand, if a 0 is received in state S0, it remains in that state with output 0.

Similarly, when in state S1, if a 0 is received as input, it remains in state S1 with a 1 as output because the number of 1’s in the input so far is odd. A 1 input takes the machine from S1 to S0 with 0 output.

If we want to carry this design forward, we need a single flip-flop to represent the two states in the FSM. We leave the complete design of this machine as an exercise to be done after reading this section (see Exercise 4–13). We show the design process on the next example, which is more complex.



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